The invention relates generally to semiconductor devices and more particularly to a semiconductor memory device that utilizes isolated storage elements that rely on hole conduction and methods for forming and using such a semiconductor memory device.
Electrically Erasable Programmable Read Only Memory (EEPROM) structures are commonly used in integrated circuits for non-volatile data storage. As is known, EEPROM device structures commonly include a floating gate that has charge storage capabilities. Charge can be forced into the floating gate structure or removed from the floating gate structure using control voltages. The conductivity of the channel underlying the floating gate is significantly altered by the presence of charge stored in the floating gate. The difference in conductivity due to a charged or uncharged floating gate can be current sensed, thus allowing binary memory states to be determined. The conductivity difference is also represented by a shift in the threshold voltage (VT) associated with the device in the two different states.
As semiconductor technology continues to evolve, the operating of voltages of semiconductor devices are often reduced in order to support low power applications. While such voltage reductions are desirable, the speed and functionality of the devices must also be maintained or improved. The lower limit for the programming and erase voltages is largely determined by the thickness of the tunnel dielectric through which charge carriers are exchanged between the floating gate and the underlying channel region.
In many prior art device structures, the floating gate is formed from a uniform layer of material such as polysilicon. In such prior art device structures, charge loss from the floating gate is dominated by leakage mediated by defects in the tunnel dielectric layer. Such charge leakage can lead to degradation of the memory state stored within the device and is therefore undesirable. In order to avoid such charge leakage, the thickness of tunnel dielectric is often increased. A thicker tunnel dielectric, however, requires higher programming and erasing voltages for storing and removing charge from the floating gate. In many cases, higher programming voltages require the implementation of charge pumps in order to increase the supply voltage to meet programming and erasing voltage requirements. Such charge pumps consume a significant amount of die area in an integrated circuit and therefore reduce memory array area efficiency and increase overall costs.
In order to reduce the required thickness in the tunnel dielectric and improve the area efficiency of the memory structures by reducing the need for charge pumps, the uniform layer of material used for the floating gate may be replaced with a plurality of isolated storage elements, which are also known as nanoclusters or nanocrystals. In combination, a plurality of isolated storage elements provide adequate charge storage capacity for the floating gate while remaining physically isolated from each other such that any leakage occurring with respect to a single isolated storage element via a local underlying defect does not cause charge to be drained from other isolated storage elements. Thus, the lack of lateral charge flow between the isolated storage elements ensures that leakage experienced by one isolated storage element does not propagate and cause charge loss in a number of isolated storage elements. As such, the tunnel dielectric can be thinned to near to the limit that would be acceptable if it were ideal and defect-free. Although there may be some leakage through defects in the oxide, such defects only cause charge loss in the isolated storage elements nearest the defects.
The majority of devices discussed in literature to date detect the presence or absence of electrons in the isolated storage elements. When programming such devices (adding charge to the isolated storage elements through the tunneling of electrons across the tunnel dielectric), the rate at which the electrons move across the tunnel dielectric is relatively fast. The nanoclusters, however, have an affinity for securely holding onto added electrons such that erasing times associated with removing the electrons from the isolated storage elements are typically much longer than the times associated with programming. This difference may be due to the presence of traps either within the isolated storage elements themselves or the surrounding material. Such traps can impede the ability for electrons that reside within those traps to utilize the applied potential to migrate across the tunnel dielectric.
The additional time required for erasing may also be due to the presence of a large number of electrons at the interface between the tunnel dielectric and the channel region for programming operations. Each of these electrons at the interface is a potential migratory electron that could move through the tunnel dielectric to add to the charged stored within the floating gate. When erasing charge stored in the floating gate, the number of electrons is more limited as the only potential migratory electrons are those stored in the floating gate. Therefore, even if the probability for movement across the tunnel dielectric for a single electron remains constant, the time over which all of the charge carriers required to erase the floating gate move across the tunnel dielectric will be greater than the time required for programming.
Memory structures that have differing programming and erasing times are undesirable in numerous applications where it may be beneficial to have the capability to program and erase individual memory cells. For example, Dynamic Random Access Memory (DRAM) type memory structures or EEPROM memory structures benefit from such individual cell programming and erasing capability. In contrast, flash memory structures are known to rely on a bulk erase operation that uniformly clears charge from the floating gate structures of the entire array such that all of the memory cells within the array are returned to an initial erased state. In such flash memory structures, longer erase times are often inconsequential, which is not the case in applications where individual memory cells need to be programmed and erased independently.
Therefore, a need exists for a memory device that utilizes isolated storage elements for charge storage, where the memory device provides symmetric programming and erasing timing characteristics.